Circuit characterization is a process of capturing circuit performance and representing the same as a black box model. SPICE simulations are performed for various input slew and output load combinations for the timing/power arcs identified from functionality and results are typically captured as a Liberty model. This Liberty model provides information on circuit performance such as delays, transition time, power, and input capacitance.
Computer-Aided-Design (CAD) systems comprise a combination of hardware and software that enable an engineer to simulate the performance of electronic systems and circuits before implementing the design in a more permanent manner. One such area that uses CAD systems frequently is the design of Application Specific Integrated Circuits (ASICs). ASICs are typically designed by using CAD system to assemble building blocks into a circuit design. Once assembled, performance characteristics of the circuit design are calculated based upon the known performance characteristics of each building block. Since the building blocks, often referred to as cells, have known performance characteristics that are typically stored in a standard cell library, the CAD system can retrieve specific data from the standard cell library to calculate parameters of the circuit design performance.
The standard cell library may contain data about several different cells. A typical standard cell library will have performance characteristics, that depends upon the magnitude of the load connected to the cell. The load is typically measured in capacitance or in proportion to capacitance. Finally, with respect to delay, the standard cell library may provide information for a logic-0 to logic-1 transition and a logic-1 to logic 0 transition.
In addition to the data described above with respect to the standard cell library, manufacturers will also typically provide data about the delay time of a cell based upon varying input slew rates. The slew rate is the rate of change of signal with respect to time. Since cells are often connected in series, the output signal of one cell is often the input signal to the next cell. Thus, the delay time of a cell will varies depending upon the slew rate of the input signal.
However, a problem with data accuracy arises because of size and data limitations of a standard cell library. Storing performance characteristics for every possible load would require a prohibitive amount of data storage space. Thus, by convention, only a few load-slew values, typically 5-8 per set of conditions, are stored for any particular cell in the standard cell library. The chosen representative load and slew values are called characterization points and are typically provided by component manufacturers. When a CAD system calls for a load-slew value that is not one of the characterization points stored in the standard cell library, one approach requires an approximation to be made between the four closest characterization points.
Current Electronic Design Automation (EDA) tools use various models for capturing circuit performance, such as delay associated with a load-slew. One conventional method uses popular model NLDM (Non-Linear Delay Model) to capture, the circuit characteristics like timing and power in the form of 2D or 3D look up tables with the input slew and output load used as the indices. The accuracy of the load-slew delay surface (or load-slew-power surface) captured in the method depends to a considerable extent on the choice of load-slew points. Determination of load-slew indices using this method requires pre-calculated data for representative cells, typically obtained by SPICE simulations. This method requires more number of points for higher accuracy.
This conventional method takes the most logical path of iteratively calculating the error between the curve and the interpolated value. The polyline is split based on the calculated error. This method obtains a reduced set of sampling points by iteratively identifying those samples whose interpolated values have a deviation greater than a specified tolerance. In this method during successive iterations, the sample with maximum deviation is added to the set of reduced samples. However, this method may not yield the minimum number of sampling points.
Consider a curve with vertex having positive ordinate as shown in FIG. 2A that illustrates a delay Vs slew for a load using a solid line. The dotted line in FIG. 2A shows the interpolated value. FIG. 2B at the bottom shows the error between the actual value and the interpolated value. FIGS. 2A and 2B illustrate result of first iteration and FIGS. 3A and 3B illustrate the result of second iteration.
It can be seen in FIGS. 2A, 2B, 3A, and 3B that, before the first iteration, only the extreme points in the abscissa (Xmin and xmax) are available in the set of final sampling points. In the first iteration (FIGS. 2A and 2B), the sampling point x1 is added to the final set of sampling points because the interpolated value can have the maximum deviation at this point. In the next iteration, shown in FIGS. 3A and 3B, points on either sides of the peak (X2 and x3) are added to the final set because the deviation is greater then the acceptable tolerance. The drawback of this method is that points are chosen with peak deviations and may not yield a minimum number of sampling points. One other drawback with this technique is that this method also fails to accommodate a three dimensional surface.
Other features of the present embodiments will be apparent from the accompanying drawings and from the detailed description that follows.